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Hughes Placement Paper2-2006 (Technical- Computer Architecture)



Paper: Hughes Placement Paper2-2006 (Technical- Computer Architecture)

    1. Which of the folowing is not correct
a. (x+y)'=x'.y' b. (x'+y')'=x.y
c. (x'.y')'=x+y d. (x'+y')'=x'.y'
Ans : [d]

2. Question on logic ckt. U have to find the output
ans. AB'+CD'+EF'

3. Output of MUX


c-----| |
c'---- | |--Y
c'---- | |
c-----| |
| |
A B (select lines)

ans. A xor B xor C

4.If X and Y are two sets. |X| and |Y| are corresponding coordinates and exact no.of functions from X to Y is 97 then
a. |X|=97 |Y|=1 b. |X|=1 |Y|=97
c. |X|=97 |Y|=97 d. .....

5. If two dies are thrown simultaneously what is the prob. of one of the dice getting face 6 ?
a. 11/36 b. 1/3 c. 12/35 d. 1/36
Ans :[a]

6. The relation ,<,on reals is
a. a partial order because of symmetric and reflexive
b Antisymmetric
c. asymmetric and non reflexive
d. anti-symm and non reflexive

7.  In C language the parameters are passed by
a. values  b. name  c. reference 

8.  Advantage of SRAM over DRAM
ans. faster

9. Daisy chaining related question (refer Z80)
a. uniform interrupt priority
b. non
c. interfacing slower peripherals

10. RAM chips arranged in 4X6 array and of 8kX4bit capacity each. How many address lines required to access each byte
a. 12 b. 16 c.15 d. 17

11.Question related to AVL trees regarding how many no. of nodes to be changed to become balanced after addition of a leaf node to a particular node.
Ans . 3

12.When following sequence is inserting the binary search tree no. of nodes in left and right sub trees 52 86 64 20 3 25 14 9 85

13.Method used for Disk searching..
a.linked list b.AVL c.B-tree d. binary tree

14.Which of the following is correct statement.
a. 1's complement can have two zero representations
b.2's ... ... represent an extra neg. number
c.2's & 1's have no difference in representing 16-bit no.

15.AX=B where A is mXn ,b&X are column matrices of order m
a. if m
b. if m=n, rank of A 
.
16.The option available in C++, not C:
a. dynamic scooping
b. declaration in the middle of code block
c. separate compiled and linked units

17.int a[4]={1,2,3,4};
int *ptr;
ptr=a;
*(a+3)=*(++ptr)+(*ptr++);
A part of code is shown. The elements in A after
the execution of this code.
a.1 2 3 4 b. 1 2 3 6
c. compilation error d.1 2 2 4 [a]

18.Critical section program segment is
a. enclosed by semaphores with P & V operations
b. deadlock avoidance
c. where shared resources are accessed

19.when head is moving back and forth, the disk scheduling
algorithm is _____
a) scan b) sstf c) fcfs 

20.how many times the loop will execute

LOOP LXI B,1526H
DCX B
JNZ LOOP
a)1526H times b) 31 c)21 d)38

21. the addressing mode in which the address of the operand is
expressed explicitly within the instruction
a)index addressing b)absolute c)indirect d) immediate

22. (A - B) U (B - A) U (A ^ C) = ?
where A,B are two sets A' , B' are compliments of A and B
a) A U B b) A ^ B c).... d).....

23. the network that does not use virtual circuit
a) IP b) X.25 c).... d).....

24. source routing bridge
a) source will route the frame
b)  frame will routed with info in header

25. cache access time 100 msec. main memory access time 800 msec
if the hit ratio is 95% , what is mean access time ...

26. the module that should be always reside in main memory is
a) loader b) link module 

27. The order of algorithm to merge the two sorted lists of lengths m and n is
a. O(m) b. O(n) c. O(m+n) d. O(log(m)+log(n))

28.A chocolate block is of 4 X 4 size. How many cuts are needed to make 1 X 1 size blocks. No simultaneous vert. & horz. cuts.

Technical:

Q. CSMA/Cd protocol used in
Ans : Ethernet

Q.  Checksum in IP packet is
Ans : Sum of the bits and 9's complement of sum

Q. Inselective repeat Max Seq is given find windowsize
i.e. Ans : (15+1)/2 = 8

Q. Main memory cache direct mapping
Ans : 64

Q. Address lines and data lines for 4K x 16
Ans : Addr 12, Data 16

Q. Infix to postsize commession uses
Ans : operator stack

Q. Printing ofstatic variable
Ans : 11

Q. Ans : 1,2,3,4 ( Program is given
array[0] = 1;
array[1] = 2;
array[2] = 3
array[3] = 4
ptr = array[0]
*(arr+3) = *(++array ) + *(array-1)++)
)
There may me some mistique in writing
the program. Check it out.
Answer is correct?

Q. One Question on Scheduling Preemptive

Q. Which of the following is not memory model
(1) buddy system (2) monitor (3) virtual ... etc.

Q. Hight balancing AVC time
Ans : 3

Q.  Simplification in boolean Algebra
Ans : xz

Q. The feature C++ have and c donot have
Ans : Variables can be declared inside also.

Q. Number of nodes with degree two in a binary tree of n leaves
Ans : n-1

Q. Difference between synchronous and asynchronous transmission

Q. Floating point representation
Ans : 2's complement

Q. Using which pin it's possible to address 16 bit addresses even though there
are only 8 address bits in 8085?
Ans: ALE

Q. Voltage gain for an amplifier is 100 while it is operating at 10 volts.
What is the O/P voltage wen i/p is 1 volt

Q. Quality factor indicates
a) Quality of inductor b) quality of capacitor c) both

Q. Question related to bridges, routers and generators, which OSI layer they correspond to.

Q. OPAmp's I/P ciurrent, O/p current and CMRR is given, what is the voltage gain

Q.  resistance increases with temperature in a) Metal b) semiconductor

Q. 16 bit mantissa and 8 bit exponent can present what maximum value?

Q. 4 bit window size in sliding window protocol, how many acknowledgements can be held?

Q. Security functionality is provided by which layer of OSI

Q. Among AM and FM which is better and why?

Q. LASt stage of TTL NAND gate is called:
Ans: Totem Pole Amplifier

Q. SR to JK flip flop conversion.
Ans: S=JQ', R=KQ

Q.  LSB of a shift register is connected to its MSB, what is formed:
Ans: RING Counter

Q. 2-3 Qns based on Demorgan's laws (identiies: (A+b)' = A'b', etc)

Q. 2 qns on Logic gates (O/p of logic gates)

Q.  Diff in IRET and RET statements of 8086

Q. How many address bytes are required to address an array of memory chips (4 * 6), each chip having 4 memory bits and 8k registers.

Q. Diff. in memory mapped and I/P O/P mapped Input/Output (Refer a book on Microprocessor)

Q. Question on pipeline architecture

Q. Question on LAPB protocol


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