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Cadence System Design Interview Pattern- VCET, Puttur, 21 February 2015


The company had come for the job profile of Analog Layout Design Engineer. Eligible branches were E&C, E&E, Mechatronics. At the end of first round, shortlisted 14 people all of E&C branches only. After that technical interview of 1-2 hrs per person and then HR interview. No GD.

Time allotted: 1 hour 15 min. Written test.

Total questions: 25

- 5 questions on Aptitude, very easy.
- 4-5 questions on Digital Logic Design and remaining on Network Analysis, Opamps and transistors.

Few questions were:

- A question on directions. A man walks 5 m south, Then turns left and walks some m, then turns right, find the displacement from initial position. Required the use of Pythagoras theorem.

- 5 consecutive numbers are there a,b,c,d,e then find the value of e in the expression a+b+e+(b-d)/b+c .

- If ab=0 find A (XOR) B

- A question on network analysis to find source resistance. Circuit diagram was given.

- To find the steady state voltage of capacitor c in the circuit. It was an RC Circuit with 2 meshes.

- A wire wound resistor is to be made of constantan whose resistivity was given. The diameter of wire was given, and the diameter of the core on which it is to be wound was given, then calculate how many turns are required for achieving a resistance of 50 OHMS.

- A question on OP Amps, a non inverting circuit was given with r=4kohm, rf=6kohm and after rf, a diode was placed with n side towards rf, calculate Vo.

- Another question on OP Amps circuit. to calculate the current in a branch and Vo

- A question to find equivalent resistance between a and b. A straight branch with 6 resistors and with some nodes between the resistors connecting to the node one after the next one. All r=1 ohm (class 12 ques if I am not wrong where you redraw and then solve)

- A question on multiplexer.

- A question on drawing the given circuit purely in terms of nand gate. Given circuit had AND, NOT and OR gate.

- A question on NAND gate sr latch. What happens when s=0 and r=0?

- A question containing two resistors in parallel, each with a diode in series with resistor. Input was v1 and v2 to resistor side, Vcc was given towards diode side, Resistors value and diode vt was given, calculate vout towards diode side. (calculate current and then voltage drop.)

- A digital circuit with AND gate and NOT gate loop, propagation delays were given, draw the waveform if some condition was given.

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